ARM Processor: AOF SDK
Assembler code
C$$code:00000024 ADD R0, R0, #1
C$$code:00000028 CMP R0, #0xC8 ; 'È'
C$$code:0000002C BLT loc_20
C$$code:00000030 ADD R1, R1, #1
C$$code:00000034 CMP R1, #0x12C
C$$code:00000038 BLT loc_10
C$$code:0000003C MOV R3, #1
C$$code:00000040
C$$code:00000040 loc_40 ; CODE XREF: x$litpool$0+90↓j
C$$code:00000040 MOV R1, #0
C$$code:00000044
C$$code:00000044 loc_44 ; CODE XREF: x$litpool$0+84↓j
C$$code:00000044 ADD R12, R1, R1,LSL#3
C$$code:00000048 ADD R12, R12, R1,LSL#4
C$$code:0000004C ADD R12, R2, R12,LSL#5
C$$code:00000050 MOV R0, #0
C$$code:00000054
C$$code:00000054 loc_54 ; CODE XREF: x$litpool$0+78↓j
C$$code:00000054 LDR LR, [R12,R0,LSL#2]
C$$code:00000058 MUL LR, R3, LR
C$$code:0000005C STR LR, [R12,R0,LSL#2]
C$$code:00000060 ADD LR, R12, R0,LSL#2
C$$code:00000064 LDR LR, [LR,#0x10]
C$$code:00000068 MUL LR, R3, LR
C$$code:0000006C STR LR, [R12,R0,LSL#2]
C$$code:00000070 ADD R0, R0, #5
C$$code:00000074 CMP R0, #0xC3 ; 'Ã'
C$$code:00000078 BLT loc_54
C$$code:0000007C ADD R1, R1, #1
C$$code:00000080 CMP R1, #0x12C
C$$code:00000084 BLT loc_44
C$$code:00000088 ADD R3, R3, #1
C$$code:0000008C CMP R3, #0x32 ; '2'
C$$code:00000090 BLT loc_40
C$$code:00000094 MOV R0, #0Last updated