# ARM Processor: Linux ELF

Assembler code

```
.text:0000107E                 VLDR            D0, [SP,#0x5E8+var_450]
.text:00001082                 VMOV            R2, R3, D0
.text:00001086                 VLDR            D0, [SP,#0x5E8+var_448]
.text:0000108A                 VMOV            R0, R1, D0
.text:0000108E                 BL              __aeabi_ddiv
.text:00001092                 VMOV            D0, R0, R1
.text:00001096                 VSTR            D0, [SP,#0x5E8+var_440]
.text:0000109A                 VLDR            D0, [SP,#0x5E8+var_440]
.text:0000109E                 VMOV            R0, R1, D0
.text:000010A2                 BL              __aeabi_d2f
.text:000010A6                 LDR             R1, =Usart1_out_DATA
.text:000010A8                 STR             R0, [R1,#0x7C] ; `vtable for'__cxxabiv1::__si_class_type_info
.text:000010AA                 LDR.W           R0, [SP,#0x5E8+var_18]
.text:000010AE                 ADDW            R0, R0, #0xCC8
.text:000010B2                 ADD.W           R0, R0, #0x400
.text:000010B6                 VLDR            D0, [R0,#0x300]
.text:000010BA                 VSTR            D0, [SP,#0x5E8+var_450]
.text:000010BE                 VLDR            D0, [SP,#0x5E8+var_450]
.text:000010C2                 BL              __hardfp_sqrt
.text:000010C6                 VSTR            D0, [SP,#0x5E8+var_448]
.text:000010CA                 LDR             R0, =glv
.text:000010CC                 VLDR            D0, [R0,#0x48]
.text:000010D0                 VSTR            D0, [SP,#0x5E8+var_450]
.text:000010D4                 VLDR            D0, [SP,#0x5E8+var_450]
.text:000010D8                 VMOV            R2, R3, D0
.text:000010DC                 VLDR            D0, [SP,#0x5E8+var_448]
.text:000010E0                 VMOV            R0, R1, D0
.text:000010E4                 BL              __aeabi_ddiv
.text:000010E8                 VMOV            D0, R0, R1
.text:000010EC                 VSTR            D0, [SP,#0x5E8+var_440]
.text:000010F0                 VLDR            D0, [SP,#0x5E8+var_440]
.text:000010F4                 VMOV            R0, R1, D0
.text:000010F8                 BL              __aeabi_d2f
.text:000010FC                 LDR             R1, =Usart1_out_DATA
.text:000010FE                 STR.W           R0, [R1,#0x80]

```


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