> For the complete documentation index, see [llms.txt](https://docs.hex-rays.com/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.hex-rays.com/core/decompiler/specification.md).

# Specification

IDA Decompilers come in 12 different flavors:

* x86 decompiler (32-bit code)
* x64 decompiler (64-bit code)
* ARM decompiler (32-bit code)
* ARM64 decompiler (64-bit code)
* PowerPC decompiler (32-bit code)
* PowerPC64 decompiler (64-bit code)
* MIPS decompiler (O32 and N32 ABI)
* MIPS64 decompiler (N64 ABI)
* RISC-V decompiler (32-bit code)
* RISC-V 64 decompiler (64-bit code)
* ARC decompiler (32-bit code)
* V850 decompiler (32-bit code)

Currently the decompiler can handle compiler generated code. Manually crafted code may be decompiled too but the results are usually worse than for compiler code.

## Current Constraints

Below are the most important limitations of our decompilers (all processors):

* exception handling is not supported (except msvc x64 c++ exceptions)
* type recovery is not performed
* global program analysis is not performed
* execution timings are not preserved
* memory access patterns are not preserved

Limitations specific to PPC:

* Vector/DFP/VSX/SPE instructions are not supported

Limitations specific to MIPS:

* O32, O64, N32, EABI32, P32(nanoMIPS) are supported
* only 32-bit FPR in O32,EABI32 and 64-bit FPR in N32,O64 are supported

Limitations specific to MIPS64:

* only N64 ABI is supported
* only 64-bit FPR are supported


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